Fibonacci Series

Fibonacci Series  #include <stdio.h> int main() {     int i, n, a1 = 0, a2 = 1, n1= 0;     printf("Enter the number of terms: ");     scanf("%d",&n);     printf("Fibonacci Series: %d, %d, ", a1, a2);     for (i=3; i <= n; ++i)     {         n1 = a1 + a2;         a1 = a2;         a2 = n1;         printf("%d,...

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Factorial of a Number

Factorial of a Number #include <stdio.h> int main() {     int n, i;     unsigned int f = 1;     printf("Enter an integer: ");     scanf("%d",&n);         for(i=1; i<=n; ++i)         {             f= f*i;                      }         printf("Factorial...

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Program to Check Leap Year

Program to Check Leap Year: #include <stdio.h> int main() {     int y;     printf("Enter a year: ");     scanf("%d",&y);     if(y%4 == 0)     {         if( y%100 == 0)         {             if ( y%400 == 0)                 printf("%d is a leap year.",...

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Check Vowel or consonant

Check Vowel or consonant: #include <stdio.h> int main() {     char c     int n1,n2;     printf("Enter any alphabet: ");     scanf("%c",&c);      n1= (c == 'a' || c == 'e' || c == 'i' || c == 'o' || c == 'u');      n2 = (c == 'A' || c == 'E' || c == 'I' || c == 'O' || c == 'U');      if (n1 || n2)         printf("%c is a vowel.",c);     else         printf("%c...

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Check Whether a Number is Even or Odd

Check Whether a Number is Even or Odd: #include <stdio.h> int main() {     int n;     printf("Enter any integer: ");     scanf("%d",&n);     if(n%2 == 0)         printf("%d is even.", n);     else         printf("%d is odd.", n);     return 0; ...

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Swap Numbers

Swap Numbers: #include <stdio.h> int main() {       int n1, n2, temp;       printf("Enter first number: ");       scanf("%d", &n1);       printf("Enter second number: ");       scanf("%d",&n2);       temp=n1;       n1 = n2;       n2=temp;       printf("\nAfter swapping, firstNumber = %d\n", n1);       printf("After...

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Print ASCII Value

 Print ASCII Value #include studio.h> #include conio.h> int main()  {     char a;     printf("Enter any character");     scanf("%c", &a);      printf("ASCII value of %c = %d", a, a);     return 0;  ...

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Add Two Integers

Add Two Integers: #include <stdio.h> int main() {     int Number1, Number2, sumofNumbers;     printf("Enter two integers: ");     scanf("%d %d",&Number1, &Number2);     sumofNumbers = Number1 + Number2;     printf(" %d",sumofNumbers);     return 0; ...

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Print an Integer Entered by the User

Print an Integer Entered by the User: #include studio.h> #include conio.h> int main() {     int n;     printf("Enter an integer: ");      scanf("%d", &);      printf("You entered: %d", n);     return 0; ...

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Print Hello Word

#include studio.h> #include conio.h>   int main()  {  printf("Hello, World! \n");           return 0; ...

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MUX

MUX 2x1 module mux2x1(y,a,b,s);     output y;     input a,b,s;   //assign y = ((!s) && a) || (s && b);   //assign y = ((~s) & a) | (s & b);   assign y = s ? b : a; endmodule MUX 4x1: module mux4x1(y,s,i);     output y;     input [1:0] s;     input [3:0] i;    //assign y = s[1]? (s[0]?i[3]:i[2]) : (s[0] ? i[1] : i[0]);    assign y = ((~s[1]) & (~s[0]) & i[0]) | ((~s[1]) & (s[0]) & i[1])      ...

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Subtractor

Half Subtractor:  module hs(d,bout,a,b);     output d,bout;     input a,b; //assign {bout,d} = a-b; assign d =  a ^ b; assign bout = ~a & b; endmodule  Full Subtractor: module fs(d,bout,a,b,c);     output d,bout;     input a,b,c; //assign {bout,d} = a - b - c;  assign d = a ^ b ^ c;  assign bout = (~a & b) | (~(a^b)&c); endmodule ...

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Gray to Binary

Gray to Binary: module g2b(b,g);     output [3:0] b;     input [3:0] g; assign b[3] = g[3]; assign b[2] = g[3] ^ g[2]; assign b[1] = g[3] ^ g[2] ^ g[1]; assign b[0] = g[3] ^ g[2] ^ g[1] ^ g[0]; endmodule ...

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Adder

Half Adder: module ha(s,c,a,b);     output s,c;     input a,b; assign s = a ^ b,        c = a & b; endmodule Full Adder: module fa(s,cout,a,b,c);     output s,cout;     input a,b,c;    assign s = a ^ b ^ c;    assign cout = (a & b) | (b & c) | (a & c); endmodule ...

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Dmux

Dmux: 1x2 module demux1x2(y,s,i);     output [1:0] y;     input s;     input i; assign y[0] = (~s) & i; assign y[1] = s & i; endmodule Dmux: 1x4: module demux1x4(y,i,s);     output [3:0] y;     input i;     input [1:0] s; assign y[0] = (~s[1] & ~ s[0] & i); assign y[1] = (~s[1] & s[0] & i); assign y[2] = (s[1] & ~s[0] & i); assign y[3] = (s[1] & s[0] & i); endmodule ...

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dec2x4

dec 2x4: module dec2x4(y,i);     output [3:0] y;     input [1:0] i; assign y[0] = ~i[1] & ~i[0],        y[1] = ~i[1] & i[0],  y[2] = i[1] & ~i[0],  y[3] = i[1] & i[0]; endmodule ...

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Binary to Gray:

 Binary to Gray: module b2g(g,b);     output [3:0] g;     input [3:0] b;  assign g[3] = b[3],         g[2] = b[3] ^ b[2],   g[1] = b[2] ^ b[1],   g[0] = b[1] ^ b[0]; endmodule ...

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And

And: module and1(c,a,b);     output [3:0]c;     input [3:0]a,b;   assign c = a && b;   // Result always Either 0 or 1;   assign c = a & b;   // gives bitwise operation   assign c = &a;   // used for reduction endmodule ...

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Add4bit

add4bit: module add4bit(s,c,a,b);     output [3:0] s;     output c;     input [3:0] a;     input [3:0] b;     assign {c,s} = a + b;   endmodule ...

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MUX

 MUX 2to1: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity mux2to1 is     Port ( a : in std_logic_vector(1 downto 0);            s : in std_logic;            y : out std_logic); end mux2to1; architecture Behavioral of mux2to1...

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JK flipflop

 JK flipflop: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity jkflipflop is     Port ( j,k,clk : in std_logic;            y : out std_logic); end jkflipflop; architecture Behavioral of jkflipflop is signal temp:std_logic:='0'; begin y<=temp; process(clk) end...

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Integer to Binary

Integer to Binary: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity ItoB is     Port ( int : in integer;            Bin : out std_logic_vector(7 downto 0)); end ItoB; architecture Behavioral of ItoB is begin process(int) variable a,b:integer; begin a:=int;...

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Half adder

Half adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity Halfadder is     Port ( aa,bb : in std_logic;            sum,carry : out std_logic); end Halfadder; architecture Behavioral of Halfadder is component anding...

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Gen comparator

Gen comparator: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity gencomparator is generic(n:integer:=16);     Port ( a,b : in std_logic_vector(n-1 downto 0);            agtb,aeqb,altb:out std_logic); end gencomparator; architecture...

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8to3 Encoder

8to3 Encoder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;                                    --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity 8to3encoder is    ...

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Demux

Demux: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.itobpack.all; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity demux is     Port ( a : in integer range 0 to 255;            y : out std_logic_vector(7 downto 0)); end demux; architecture Behavioral of...

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D fipflop

D fipflop: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity dfipflop is     Port ( d,clk : in std_logic;            y : out std_logic); end dfipflop; architecture Behavioral of dfipflop is begin process(clk) begin if(clk='1'...

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Full adder

Full adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity Fulladder is port(a,b,Cin:in std_logic;                  ss,ca:out std_logic); end Fulladder; architecture Behavioral of Fulladder is component...

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Comparator:

Comparator: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity comparator is     Port ( a,b : in std_logic_vector(3 downto 0);            agtb,altb,aeqb : out std_logic); end comparator; architecture Behavioral of comparator...

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Clk divider

Clk divider: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity clkdivider is     Port ( clk : in std_logic;            y: out std_logic); end clkdivider; architecture Behavioral of clkdivider is signal nclk:std_logic:='0'; begin y<=nclk; process(clk) variable...

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BCD on7segment

BCD on7segment: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity bcdon7segment is     Port ( clk,rst : in std_logic;            y : out std_logic_vector(6 downto 0)); end bcdon7segment; architecture Behavioral of bcdon7segment...

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BCD counter

BCD  counter: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity bcdcounter is     Port ( clk,rst : in std_logic;            y : out std_logic_vector(3 downto 0)); end bcdcounter; architecture Behavioral of bcdcounter...

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ALU

ALU: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity alu is     Port ( a,b : in std_logic_vector(7 downto 0);            y : out std_logic_vector(7 downto 0)); end alu; architecture Behavioral of alu is type instr...

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3bit Counter:

3bit Counter: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --  Uncomment the following lines to use the declarations that are --  provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity counter is     Port ( clk,rst : in std_logic;            y : out std_logic_vector(2 downto 0)); end counter; architecture Behavioral of counter is type...

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Interfacing with PIC

Interfacing of led with PIC Interfacing of 7 segment with PIC Interfacing of lcd with PIC Interfacing of Keypad with PIC Timer with PIC ...

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Timer with PIC

Program: #include<pic.h> #include<htc.h> #define __16f877A_H __CONFIG(WDTE_OFF&LVP_OFF&FOSC_HS&PWRTE_ON); void main() { unsigned int i; TRISB=0x00; OPTION_REG=0x01; PORTB=0xff; while(1) { for(i=0;i<3921;i++) { TMR0=0x00; while(!TMR0IF); TMR0IF=0; } TMR0=0x6f; //while(!TMR0IF); //TMR0IF=0; PORTB=~PORTB; } } ...

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Interfacing of Keypad with PIC

Matrix Keypad: Matrix Keypads are commonly used in calculators, telephones etc where a number of input switches are required. We know that matrix keypad is made by arranging push button switches in row and columns. In the straight forward way to connect a 4×4 keypad (16 switches) to a microcontroller we need 16 inputs pins. But by connecting switches in the following way we can read the status of each switch using 8 pins of the microcontroller. Program: #include<pic.h> #include<htc.h> #define...

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Interfacing of lcd with PIC

LCD (Liquid Crystal Display) : LCD screen is an electronic display module and find a wide range of applications. A 16x2 LCD display is very basic module and is very commonly used in various devices and circuits. These modules are preferred over seven segment and other multi segment LED's. The reasons being: LCDs are economical; easily programmable; have no limitation of displaying special & even custom character (unlike...

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