Fibonacci Series

Fibonacci Series 

#include <stdio.h>

int main()

{

    int i, n, a1 = 0, a2 = 1, n1= 0;

    printf("Enter the number of terms: ");

    scanf("%d",&n);

    printf("Fibonacci Series: %d, %d, ", a1, a2);

    for (i=3; i <= n; ++i)

    {

        n1 = a1 + a2;

        a1 = a2;

        a2 = n1;

        printf("%d, ",n1);

    }

    return 0;

}

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Factorial of a Number

Factorial of a Number

#include <stdio.h>

int main()

{

    int n, i;

    unsigned int f = 1;

    printf("Enter an integer: ");

    scanf("%d",&n);

        for(i=1; i<=n; ++i)

        {

            f= f*i;             

        }

        printf("Factorial of %d = %d", n, f);

   

    return 0;

}

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Program to Check Leap Year

Program to Check Leap Year:

#include <stdio.h>

int main()

{

    int y;

    printf("Enter a year: ");

    scanf("%d",&y);

    if(y%4 == 0)

    {

        if( y%100 == 0)

        {

            if ( y%400 == 0)

                printf("%d is a leap year.", y);

            else

                printf("%d is not a leap year.", y);

        }

        else

            printf("%d is a leap year.", y );

    }

    else

        printf("%d is not a leap year.", y);

    return 0;

}

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Check Vowel or consonant

Check Vowel or consonant:

#include <stdio.h>

int main()

{

    char c

    int n1,n2;

    printf("Enter any alphabet: ");

    scanf("%c",&c);

     n1= (c == 'a' || c == 'e' || c == 'i' || c == 'o' || c == 'u');

     n2 = (c == 'A' || c == 'E' || c == 'I' || c == 'O' || c == 'U');

     if (n1 || n2)

        printf("%c is a vowel.",c);

    else

        printf("%c is a consonant.",c);

    return 0;

}

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Check Whether a Number is Even or Odd

Check Whether a Number is Even or Odd:

#include <stdio.h>

int main()

{

    int n;

    printf("Enter any integer: ");

    scanf("%d",&n);

    if(n%2 == 0)

        printf("%d is even.", n);

    else

        printf("%d is odd.", n);

    return 0;

}

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Swap Numbers

Swap Numbers:

#include <stdio.h>

int main()

{

      int n1, n2, temp;

      printf("Enter first number: ");

      scanf("%d", &n1);

      printf("Enter second number: ");

      scanf("%d",&n2);

      temp=n1;

      n1 = n2;

      n2=temp;

      printf("\nAfter swapping, firstNumber = %d\n", n1);

      printf("After swapping, secondNumber = %.d", n2);

      return 0;

}

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Print ASCII Value

 Print ASCII Value

#include studio.h>

#include conio.h>

int main()

 {

    char a;

    printf("Enter any character");

    scanf("%c", &a); 

    printf("ASCII value of %c = %d", a, a);

    return 0;

 }

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Add Two Integers

Add Two Integers:

#include <stdio.h>

int main()

{

    int Number1, Number2, sumofNumbers;

    printf("Enter two integers: ");

    scanf("%d %d",&Number1, &Number2);

    sumofNumbers = Number1 + Number2;

    printf(" %d",sumofNumbers);

    return 0;

}

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Print an Integer Entered by the User

Print an Integer Entered by the User:

#include studio.h>

#include conio.h>

int main()

{

    int n;

    printf("Enter an integer: "); 

    scanf("%d", &); 

    printf("You entered: %d", n);

    return 0;

}

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Print Hello Word

#include studio.h>

#include conio.h>

  int main() 

{

 printf("Hello, World! \n");

          return 0;

}

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MUX

MUX 2x1

module mux2x1(y,a,b,s);
    output y;
    input a,b,s;
  //assign y = ((!s) && a) || (s && b);
  //assign y = ((~s) & a) | (s & b);
  assign y = s ? b : a;
endmodule

MUX 4x1:

module mux4x1(y,s,i);

    output y;

    input [1:0] s;

    input [3:0] i;

   //assign y = s[1]? (s[0]?i[3]:i[2]) : (s[0] ? i[1] : i[0]);

   assign y = ((~s[1]) & (~s[0]) & i[0]) | ((~s[1]) & (s[0]) & i[1])

               | ((s[1]) & (~s[0]) & i[2]) | ((s[1]) & (s[0]) & i[3]);

endmodule

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Subtractor

Half Subtractor: 

module hs(d,bout,a,b);
    output d,bout;
    input a,b;
//assign {bout,d} = a-b;
assign d =  a ^ b;
assign bout = ~a & b;

endmodule

 Full Subtractor:

module fs(d,bout,a,b,c);

    output d,bout;

    input a,b,c;

//assign {bout,d} = a - b - c;

 assign d = a ^ b ^ c;

 assign bout = (~a & b) | (~(a^b)&c);

endmodule

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Gray to Binary

Gray to Binary:

module g2b(b,g);
    output [3:0] b;
    input [3:0] g;

assign b[3] = g[3];
assign b[2] = g[3] ^ g[2];
assign b[1] = g[3] ^ g[2] ^ g[1];
assign b[0] = g[3] ^ g[2] ^ g[1] ^ g[0];


endmodule

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Adder

Half Adder:

module ha(s,c,a,b);
    output s,c;
    input a,b;

assign s = a ^ b,
       c = a & b;

endmodule

Full Adder:

module fa(s,cout,a,b,c);
    output s,cout;
    input a,b,c;

   assign s = a ^ b ^ c;
   assign cout = (a & b) | (b & c) | (a & c);


endmodule

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Dmux

Dmux: 1x2

module demux1x2(y,s,i);
    output [1:0] y;
    input s;
    input i;

assign y[0] = (~s) & i;
assign y[1] = s & i;

endmodule

Dmux: 1x4:

module demux1x4(y,i,s);

    output [3:0] y;

    input i;

    input [1:0] s;

assign y[0] = (~s[1] & ~ s[0] & i);

assign y[1] = (~s[1] & s[0] & i);

assign y[2] = (s[1] & ~s[0] & i);

assign y[3] = (s[1] & s[0] & i);

endmodule

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dec2x4

dec 2x4:

module dec2x4(y,i);
    output [3:0] y;
    input [1:0] i;
assign y[0] = ~i[1] & ~i[0],
       y[1] = ~i[1] & i[0],
 y[2] = i[1] & ~i[0],
 y[3] = i[1] & i[0];

endmodule

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Binary to Gray:

 Binary to Gray:

module b2g(g,b);
    output [3:0] g;
    input [3:0] b;

 assign g[3] = b[3],
        g[2] = b[3] ^ b[2],
  g[1] = b[2] ^ b[1],
  g[0] = b[1] ^ b[0];

endmodule

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And

And:

module and1(c,a,b);
    output [3:0]c;
    input [3:0]a,b;

  assign c = a && b;   // Result always Either 0 or 1;
  assign c = a & b;   // gives bitwise operation
  assign c = &a;   // used for reduction

endmodule

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Add4bit

add4bit:

module add4bit(s,c,a,b);
    output [3:0] s;
    output c;
    input [3:0] a;
    input [3:0] b;

    assign {c,s} = a + b;

  endmodule

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MUX

 MUX 2to1:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux2to1 is
    Port ( a : in std_logic_vector(1 downto 0);
           s : in std_logic;
           y : out std_logic);
end mux2to1;

architecture Behavioral of mux2to1 is

begin
y<=(a(0) and (not s)) or (a(1) and s);

end Behavioral;

MUX 4to1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux4to1 is

    Port ( aa : in std_logic_vector(3 downto 0);

           ss : in std_logic_vector(1 downto 0);

           yy : out std_logic);

end mux4to1;

architecture Behavioral of mux4to1 is

component mux2to1 is

port(a:in std_logic_vector(1 downto 0);

s:in std_logic;

y:out std_logic);

end component;

signal m:std_logic_vector(1 downto 0);

begin

 a1:mux2to1 port map(aa(1 downto 0),ss(0),m(0));

 a2:mux2to1 port map(aa(3 downto 2),ss(0),m(1));

 a3:mux2to1 port map(m,ss(1),yy);

end Behavioral;

MUX8to1:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux8to1 is

    Port ( aaa : in std_logic_vector(7 downto 0);

           sss : in std_logic_vector(2 downto 0);

           yyy : out std_logic);

end mux8to1;

architecture Behavioral of mux8to1 is

component mux4to1 is

port(aa:in std_logic_vector(3 downto 0);

ss:in std_logic_vector(1 downto 0);

yy:out std_logic);

end component;

component mux2to1 is

port(a:in std_logic_vector(1 downto 0);

s:in std_logic;

y:out std_logic);

end component;

signal m:std_logic_vector(1 downto 0);

begin

a1:mux4to1 port map(aa(3 downto 0),ss(1 downto 0),m(0));

a2:mux4to1 port map(aa(7 downto 4,ss(1 downto 0),m(1));

a3:mux2to1 port map(m,ss(2),yy);

end Behavioral;

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JK flipflop

 JK flipflop:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jkflipflop is
    Port ( j,k,clk : in std_logic;
           y : out std_logic);
end jkflipflop;

architecture Behavioral of jkflipflop is
signal temp:std_logic:='0';
begin
y<=temp;
process(clk)

end Behavioral;

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Integer to Binary

Integer to Binary:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ItoB is
    Port ( int : in integer;
           Bin : out std_logic_vector(7 downto 0));
end ItoB;

architecture Behavioral of ItoB is
begin
process(int)
variable a,b:integer;
begin
a:=int;
b:=a;
for i in 0 to 7 loop
a:=a rem 2;
if(a=1)then
Bin(i)<='1';
else
Bin(i)<='0';
end if;
b:=b/2;
a:=b;
end loop;
end process;


end Behavioral;

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Half adder

Half adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Halfadder is

    Port ( aa,bb : in std_logic;

           sum,carry : out std_logic);

end Halfadder;

architecture Behavioral of Halfadder is

component anding is

port(a,b:in std_logic;

                 y: out std_logic);

end component;

component xoring is

port(x,y:in std_logic;

                 p:out std_logic);

end component;

begin

u1:anding port map(aa,bb,carry);

u2:xoring port map(aa,bb,sum);

end Behavioral;

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Gen comparator

Gen comparator:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity gencomparator is

generic(n:integer:=16);

    Port ( a,b : in std_logic_vector(n-1 downto 0);

           agtb,aeqb,altb:out std_logic);

end gencomparator;

architecture Behavioral of gencomparator is

begin

process(a,b)

begin

for i in n-1 downto 0 loop

if(a(i)='1' and b(i)='0')then

agtb<='1';

aeqb<='0';

altb<='0';

exit;

elsif(a(i)='0' and b(i)='1')then

agtb<='0';

altb<='1';

aeqb<='0';

exit;

elsif(i=0)then

agtb<='0';

altb<='0';

aeqb<='1';

end if;

end loop;

end process;

end Behavioral;

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8to3 Encoder

8to3 Encoder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

                                  

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity 8to3encoder is

    Port ( b : in std_logic_vector(7 downto 0);

           y : in std_logic_vector(2 downto 0));

end 8to3encoder;

architecture Behavioral of 8to3encoder is

begin

end if;

end loop;

end Behavioral;

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Demux

Demux:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.itobpack.all;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity demux is

    Port ( a : in integer range 0 to 255;

           y : out std_logic_vector(7 downto 0));

end demux;

architecture Behavioral of demux is

begin

process(a)

begin

y<=itob(a);

end process;

end Behavioral;

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D fipflop

D fipflop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dfipflop is

    Port ( d,clk : in std_logic;

           y : out std_logic);

end dfipflop;

architecture Behavioral of dfipflop is

begin

process(clk)

begin

if(clk='1' and clk'event)then

y<=d;

end if;

end process;

end Behavioral;

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Full adder

Full adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Fulladder is

port(a,b,Cin:in std_logic;

                 ss,ca:out std_logic);

end Fulladder;

architecture Behavioral of Fulladder is

component halfadder is

port(aa,bb:in std_logic;

                sum,carry:out std_logic);

end component;

signal h1s,h1c,h2c:std_logic;

begin

u1:halfadder port map(aa=>a,sum=>h1s,carry=>h1c,bb=>b);

u2:halfadder port map(aa=>h1s,bb=>Cin,sum=>ss,carry=>h2c);

ca<=h1c or h2c;

end Behavioral;

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Comparator:

Comparator:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity comparator is

    Port ( a,b : in std_logic_vector(3 downto 0);

           agtb,altb,aeqb : out std_logic);

end comparator;

architecture Behavioral of comparator is

begin

process(a,b)

begin

for i in 3 downto 0 loop

if(a(i)='1' and b(i)='0')then

agtb<='1';

aeqb<='0';

altb<='0';

exit;

elsif(a(i)='0' and b(i)='1')then

agtb<='0';

altb<='1';

aeqb<='0';

exit;

elsif(i=0)then

agtb<='0';

altb<='0';

aeqb<='1';

end if;

end loop;

end process;

end Behavioral;

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Clk divider

Clk divider:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity clkdivider is

    Port ( clk : in std_logic;

           y: out std_logic);

end clkdivider;

architecture Behavioral of clkdivider is

signal nclk:std_logic:='0';

begin

y<=nclk;

process(clk)

variable i:integer:=0;

begin

if(clk='1' and clk'event)then

i:=i+1;

if(i=4000000)then

nclk<=not(nclk);

i:=0;

end if;

end if;

end process;

end Behavioral;

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BCD on7segment

BCD on7segment:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bcdon7segment is

    Port ( clk,rst : in std_logic;

           y : out std_logic_vector(6 downto 0));

end bcdon7segment;

architecture Behavioral of bcdon7segment is

signal a:std_logic_vector(3 downto 0);

begin

process(a)

begin

case a is

when "0000"=> y<="0111111";

when "0001"=> y<="0000110";

when "0010"=> y<="1011011";

when "0011"=> y<="1001111";

when "0100"=> y<="1100111";

when "0101"=> y<="1101101";

when "0110"=> y<="1111100";

when "0111"=> y<="0000111";

when "1000"=> y<="1111111";

when "1001"=> y<="1101111";

end case;

end process;

end Behavioral;

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BCD counter

BCD  counter:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bcdcounter is

    Port ( clk,rst : in std_logic;

           y : out std_logic_vector(3 downto 0));

end bcdcounter;

architecture Behavioral of bcdcounter is

signal count:std_logic_vector(3 downto 0):=X"0";

begin

y<=count;

process(clk,rst)

begin

if(rst='1')then

count<=X"0";

elsif(count="1001")then

count<=X"0";

elsif(clk='1' and clk'event)then

count<=count+X"1";

end if;

end process;

end Behavioral;

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ALU

ALU:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity alu is

    Port ( a,b : in std_logic_vector(7 downto 0);

           y : out std_logic_vector(7 downto 0));

end alu;

architecture Behavioral of alu is

type instr is(add,subb,ANL,ORL,CPL,INC,DEC);

signal inst:instr;

begin

process(a,b,inst)

begin

case inst is

when add=> y<=a+b;       

when subb=> y<=a-b;

when ANL=> y<=a and b;

when ORL=> y<=a or b;

when CPL=> y<=not a;

when INC=> y<= a+X"01";

when DEC=> y<= a-X"01";

when others=> y<="ZZZZZZZZ";

end case;

end process;

end Behavioral;

Anding:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity anding is

    Port ( a,b : in std_logic;

           y : out std_logic);

end anding;

architecture Behavioral of anding is

begin

y<=a and b;

end Behavioral;

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3bit Counter:

3bit Counter:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter is

    Port ( clk,rst : in std_logic;

           y : out std_logic_vector(2 downto 0));

end counter;

architecture Behavioral of counter is

type state is(st0,st1,st2,st3,st4,st5,st6,st7);

signal ps,ns:state;

begin

process(clk)

begin

if(clk='1' and clk'event)then

if(rst='1')then

ps<=st0;

else

ps<=ns;

end if;

else

null;

end if;

end process;

process(ps)

begin

case ps is

when st0=> y<="000"; ns<=st1;

when st1=> y<="001"; ns<=st2;

when st2=> y<="010"; ns<=st3;

when st3=> y<="011"; ns<=st4;

when st4=> y<="100"; ns<=st5;

when st5=> y<="101"; ns<=st6;

when st6=> y<="110"; ns<=st7;

when st7=> y<="111"; ns<=st0;

end case;

end process;

end Behavioral;

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Interfacing with PIC

• Interfacing of led with PIC

• Interfacing of 7 segment with PIC

• Interfacing of lcd with PIC

• Interfacing of Keypad with PIC

• Timer with PIC

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Timer with PIC

Program:

#include<pic.h>

#include<htc.h>

#define __16f877A_H

__CONFIG(WDTE_OFF&LVP_OFF&FOSC_HS&PWRTE_ON);

void main()

{

unsigned int i;

TRISB=0x00;

OPTION_REG=0x01;

PORTB=0xff;

while(1)

{

for(i=0;i<3921;i++)

{

TMR0=0x00;

while(!TMR0IF);

TMR0IF=0;

}

TMR0=0x6f;

//while(!TMR0IF);

//TMR0IF=0;

PORTB=~PORTB;

}

}

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Interfacing of Keypad with PIC

Matrix Keypad: Matrix Keypads are commonly used in calculators, telephones etc where a number of input switches are required. We know that matrix keypad is made by arranging push button switches in row and columns. In the straight forward way to connect a 4×4 keypad (16 switches) to a microcontroller we need 16 inputs pins. But by connecting switches in the following way we can read the status of each switch using 8 pins of the microcontroller.

Program:

#include<pic.h>

#include<htc.h>

#define __PIC16f877A_H

__CONFIG(WDTE_OFF&FOSC_HS&PWRTE_ON&LVP_OFF);

#include"lcd_header.h"

void main()

{

TRISB=0x00;

TRISC=0x00;

TRISD=0x00;

unsigned int i,a,b;

init();

while(1)

{

PORTC=0x0F;

a=PORTC;

PORTC=0xF0;

b=PORTC;

i=a|b;

switch(i)

{

case 0xE7:

  datta('0');

  delay(5000);

  break;

case 0xEB:

  datta('1');

  delay(5000);

  break;

case 0xED:

  datta('2');

  delay(5000);

  break;

case 0xEE:

  datta('3');

  delay(5000);

  break;

case 0xD7:

  datta('4');

  delay(5000);

  break;

case 0xDB:

  datta('5');

  delay(5000);

  break;

case 0xDD:

  datta('6');

  delay(5000);

  break;

case 0xDE:

  datta('7');

  delay(5000);

  break;

case 0xB7:

  datta('8');

  delay(5000);

  break;

case 0xBB:

  datta('9');

  delay(5000);

  break;

case 0xBD:

  datta('A');

  delay(5000);

  break;

case 0xBE:

  datta('B');

  delay(5000);

  break;

case 0x77:

  datta('C');

  delay(5000);

  break;

case 0x7B:

  datta('D');

  delay(5000);

  break;

case 0x7D:

  datta('E');

  delay(5000);

  break;

case 0x7E:

  datta('F');

  delay(5000);

  break;

default:

            PORTC=0x00;

break;

}

}

}

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Interfacing of lcd with PIC

LCD (Liquid Crystal Display) : LCD screen is an electronic display module and find a wide range of applications. A 16x2 LCD display is very basic module and is very commonly used in various devices and circuits. These modules are preferred over seven segment and other multi segment LED's. The reasons being: LCDs are economical; easily programmable; have no limitation of displaying special & even custom character (unlike in seven segments), animation and so on. A 16x2 LCD means it can display 16 characters per line and there are 2 such lines. In this LCD each character is displayed in 5x7 pixel matrix. This LCD has two registers, namely, Command and Data.

                      The command register stores the command instructions given to the LCD. A command is an instruction given to LCD to do a predefined task like initializing it, clearing its screen, setting the cursor position, controlling display etc. The data register stores the data to be displayed on the LCD. The data is the ASCII value of the character to be displayed on the LCD. Click to learn more about internal structure of a LCD.

           

Block Diagram of LCD:

LCD stands for liquid crystal display. They come in many sizes 8x1 , 8x2 ,10x2, 16x1 , 16x2 , 16x4 , 20x2 , 20x4 ,24x2 , 30x2 , 32x2 , 40x2 etc . Many multinational companies like Philips Hitachi Panasonic make their own special kind of lcd's to be used in their products. All the lcd’s performs the same functions (display characters numbers special characters ASCII characters etc).Their programming is also same and they all have same 14 pins (0-13) or 16 pins (0 to 15). 

ALL LCDs have

• Eight(8) Data pins
• VCC (Apply 5v here)
• GND (Ground this pin)
• RS (Register select)
• RW (read - write)
• EN (Enable)
• V0 (Set Lcd contrast)

8-Data pins carries 8-bit data or command from an external unit such as microcontroller. 

Lcd have two registers:

1)    Command Register 

2)    Data Register

1        1)      Command Register:   When we send commands to lcd these commands go to Command register and are processed their. Commands with their full description are given in the picture below.
  When RS=0    Command Register is Selected.

2) Data Register: When we send Data to lcd it goes to data register and is processed their.

  When RS=1    Data Register is selected.

Pin diagram of  LCD:

Pin description:

Pin No:	Name	Function
1	VSS	This pin must be connected to the ground
2	VCC	Positive supply voltage pin (5V DC)
3	VEE	Contrast adjustment
4	RS	Register selection
5	R/W	Read or write
6	E	Enable
7	DB0	Data
8	DB1	Data
9	DB2	Data
10	DB3	Data
11	DB4	Data
12	DB5	Data
13	DB6	Data
14	DB7	Data
15	LED+	Back light LED+
16	LED-	Back light LED-

16×2 LCD module commands:

16×2 LCD module has a set of preset command instructions. Each command will make the module to do a particular task. These commands are very important for displaying data in LCD. The list of commands given below:

Command	Function
0F	For switching on LCD, blinking the cursor.
1	Clearing the screen
2	Return home.
4	Decrement cursor
6	Increment cursor
E	Display on and also cursor on
80	Force cursor to beginning of the first line
C0	Force cursor to beginning of second line
38	Use two lines and 5x7 matrix
83	Cursor line 1 position 3
3C	Activate second line
0C3	Jump to second line position 3
0C1	Jump to second line position1

LCD initialization:

The steps that has to be done for initializing the LCD display is given below and these steps are common for almost all applications.

§  Send 38H to the 8 bit data line for initialization

§  Send 0FH for making LCD ON, cursor ON and cursor blinking ON.

§  Send 06H for incrementing cursor position.

§  Send 01H for clearing the display and return the cursor.

Sending data to the LCD:

The steps for sending data to the LCD module is given below. I have already said that the LCD module has pins namely RS, R/W and E. It is the logic state of these pins that make the module to determine whether a given data input  is a command or data to be displayed.

- Make R/W low.

-  Make RS=0 if data byte is a command and make RS=1 if the data byte is a data to be displayed.

-  Place data byte on the data register.

-  Pulse E from high to low.

-   Repeat above steps for sending another data.

Program: 

Display 'a' on the LCD:

#include<pic.h>

#include<htc.h>

#define __PIC16f877A_H

__CONFIG(WDTE_OFF&FOSC_HS&PWRTE_ON&LVP_OFF);

void delay(unsigned int t)

{

while(t--);

}

void datta(unsigned int a)

{

PORTB=a;

PORTD=0x05;

delay(300);

PORTD=0x01;

}

void command(unsigned int s)

{

PORTB=s;

PORTD=0x04;

delay(300);

PORTD=0x00;

}

void init()

{

command(0x38);

delay(1000);

command(0x01);

delay(1000);

command(0x0E);

delay(1000);

command(0x80);

delay(1000);

}

void main()

{

TRISB=0x00;

TRISD=0x00;

init();

while(1)

{

datta('a');

while(1);

}

}

Display "welcome" on the LCD:

#include<pic.h>

#include<htc.h>

#define __PIC16f877A_H

__CONFIG(WDTE_OFF&FOSC_HS&PWRTE_ON&LVP_OFF);

void delay(unsigned int t)

{

while(t--);

}

void datta(unsigned int a)

{

PORTB=a;

PORTD=0x05;

delay(300);

PORTD=0x01;

}

void command(unsigned int s)

{

PORTB=s;

PORTD=0x04;

delay(300);

PORTD=0x00;

}

void init()

{

command(0x38);

delay(1000);

command(0x01);

delay(1000);

command(0x0E);

delay(1000);

command(0x80);

delay(1000);

}

void main()

{

TRISB=0x00;

TRISD=0x00;

unsigned char a[8]={"Welcome"};

unsigned int i;

init();

while(1)

{

for(i=0;i<8;i++)

{

datta(a[i]);

}

while(1);

}

}

Display "welcome" on the LCD using pointer:

#include<pic.h>

#include<htc.h>

#define __PIC16f877A_H

__CONFIG(WDTE_OFF&FOSC_HS&PWRTE_ON&LVP_OFF);

void delay(unsigned int t)

{

while(t--);

}

void datta(unsigned int a)

{

PORTB=a;

PORTD=0x05;

delay(300);

PORTD=0x01;

}

void command(unsigned int s)

{

PORTB=s;

PORTD=0x04;

delay(300);

PORTD=0x00;

}

void init()

{

command(0x38);

delay(1000);

command(0x01);

delay(1000);

command(0x0E);

delay(1000);

command(0x80);

delay(1000);

}

void strng(unsigned char *p)

{ 

while(1)

{

while(*p!='\0')

{

datta(*p);

p++;

}

while(1);

}

}

void main()

{

TRISB=0x00;

TRISD=0x00;

unsigned int i;

init();

strng("welcome");

}

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