Gen comparator:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the
following lines to use the declarations that are
-- provided for
instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gencomparator is
generic(n:integer:=16);
Port ( a,b : in
std_logic_vector(n-1 downto 0);
agtb,aeqb,altb:out std_logic);
end gencomparator;
architecture Behavioral of gencomparator is
begin
process(a,b)
begin
for i in n-1 downto 0 loop
if(a(i)='1' and b(i)='0')then
agtb<='1';
aeqb<='0';
altb<='0';
exit;
elsif(a(i)='0' and b(i)='1')then
agtb<='0';
altb<='1';
aeqb<='0';
exit;
elsif(i=0)then
agtb<='0';
altb<='0';
aeqb<='1';
end if;
end loop;
end process;
end Behavioral;
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