ALU

ALU:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity alu is

    Port ( a,b : in std_logic_vector(7 downto 0);

           y : out std_logic_vector(7 downto 0));

end alu;

architecture Behavioral of alu is

type instr is(add,subb,ANL,ORL,CPL,INC,DEC);

signal inst:instr;

begin

process(a,b,inst)

begin

case inst is

when add=> y<=a+b;       

when subb=> y<=a-b;

when ANL=> y<=a and b;

when ORL=> y<=a or b;

when CPL=> y<=not a;

when INC=> y<= a+X"01";

when DEC=> y<= a-X"01";

when others=> y<="ZZZZZZZZ";

end case;

end process;

end Behavioral;

Anding:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity anding is

    Port ( a,b : in std_logic;

           y : out std_logic);

end anding;

architecture Behavioral of anding is

begin

y<=a and b;

end Behavioral;