And:
module and1(c,a,b);
output [3:0]c;
input [3:0]a,b;
assign c = a && b; // Result always Either 0 or 1;
assign c = a & b; // gives bitwise operation
assign c = &a; // used for reduction
endmodule
Tuesday, 2 August 2016
And
module and1(c,a,b);
output [3:0]c;
input [3:0]a,b;
assign c = a && b; // Result always Either 0 or 1;
assign c = a & b; // gives bitwise operation
assign c = &a; // used for reduction
endmodule
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if you have any doubt please let me know