MUX

 MUX 2to1:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux2to1 is
    Port ( a : in std_logic_vector(1 downto 0);
           s : in std_logic;
           y : out std_logic);
end mux2to1;

architecture Behavioral of mux2to1 is

begin
y<=(a(0) and (not s)) or (a(1) and s);

end Behavioral;

MUX 4to1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux4to1 is

    Port ( aa : in std_logic_vector(3 downto 0);

           ss : in std_logic_vector(1 downto 0);

           yy : out std_logic);

end mux4to1;

architecture Behavioral of mux4to1 is

component mux2to1 is

port(a:in std_logic_vector(1 downto 0);

s:in std_logic;

y:out std_logic);

end component;

signal m:std_logic_vector(1 downto 0);

begin

 a1:mux2to1 port map(aa(1 downto 0),ss(0),m(0));

 a2:mux2to1 port map(aa(3 downto 2),ss(0),m(1));

 a3:mux2to1 port map(m,ss(1),yy);

end Behavioral;

MUX8to1:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux8to1 is

    Port ( aaa : in std_logic_vector(7 downto 0);

           sss : in std_logic_vector(2 downto 0);

           yyy : out std_logic);

end mux8to1;

architecture Behavioral of mux8to1 is

component mux4to1 is

port(aa:in std_logic_vector(3 downto 0);

ss:in std_logic_vector(1 downto 0);

yy:out std_logic);

end component;

component mux2to1 is

port(a:in std_logic_vector(1 downto 0);

s:in std_logic;

y:out std_logic);

end component;

signal m:std_logic_vector(1 downto 0);

begin

a1:mux4to1 port map(aa(3 downto 0),ss(1 downto 0),m(0));

a2:mux4to1 port map(aa(7 downto 4,ss(1 downto 0),m(1));

a3:mux2to1 port map(m,ss(2),yy);

end Behavioral;