D fipflop

D fipflop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dfipflop is

    Port ( d,clk : in std_logic;

           y : out std_logic);

end dfipflop;

architecture Behavioral of dfipflop is

begin

process(clk)

begin

if(clk='1' and clk'event)then

y<=d;

end if;

end process;

end Behavioral;