3bit Counter:

3bit Counter:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter is

    Port ( clk,rst : in std_logic;

           y : out std_logic_vector(2 downto 0));

end counter;

architecture Behavioral of counter is

type state is(st0,st1,st2,st3,st4,st5,st6,st7);

signal ps,ns:state;

begin

process(clk)

begin

if(clk='1' and clk'event)then

if(rst='1')then

ps<=st0;

else

ps<=ns;

end if;

else

null;

end if;

end process;

process(ps)

begin

case ps is

when st0=> y<="000"; ns<=st1;

when st1=> y<="001"; ns<=st2;

when st2=> y<="010"; ns<=st3;

when st3=> y<="011"; ns<=st4;

when st4=> y<="100"; ns<=st5;

when st5=> y<="101"; ns<=st6;

when st6=> y<="110"; ns<=st7;

when st7=> y<="111"; ns<=st0;

end case;

end process;

end Behavioral;