Clk divider

Clk divider:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity clkdivider is

    Port ( clk : in std_logic;

           y: out std_logic);

end clkdivider;

architecture Behavioral of clkdivider is

signal nclk:std_logic:='0';

begin

y<=nclk;

process(clk)

variable i:integer:=0;

begin

if(clk='1' and clk'event)then

i:=i+1;

if(i=4000000)then

nclk<=not(nclk);

i:=0;

end if;

end if;

end process;

end Behavioral;