Integer to Binary

Integer to Binary:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ItoB is
    Port ( int : in integer;
           Bin : out std_logic_vector(7 downto 0));
end ItoB;

architecture Behavioral of ItoB is
begin
process(int)
variable a,b:integer;
begin
a:=int;
b:=a;
for i in 0 to 7 loop
a:=a rem 2;
if(a=1)then
Bin(i)<='1';
else
Bin(i)<='0';
end if;
b:=b/2;
a:=b;
end loop;
end process;


end Behavioral;