Full adder

Full adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Fulladder is

port(a,b,Cin:in std_logic;

                 ss,ca:out std_logic);

end Fulladder;

architecture Behavioral of Fulladder is

component halfadder is

port(aa,bb:in std_logic;

                sum,carry:out std_logic);

end component;

signal h1s,h1c,h2c:std_logic;

begin

u1:halfadder port map(aa=>a,sum=>h1s,carry=>h1c,bb=>b);

u2:halfadder port map(aa=>h1s,bb=>Cin,sum=>ss,carry=>h2c);

ca<=h1c or h2c;

end Behavioral;