JK flipflop

 JK flipflop:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jkflipflop is
    Port ( j,k,clk : in std_logic;
           y : out std_logic);
end jkflipflop;

architecture Behavioral of jkflipflop is
signal temp:std_logic:='0';
begin
y<=temp;
process(clk)

end Behavioral;