BCD on7segment

BCD on7segment:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bcdon7segment is

    Port ( clk,rst : in std_logic;

           y : out std_logic_vector(6 downto 0));

end bcdon7segment;

architecture Behavioral of bcdon7segment is

signal a:std_logic_vector(3 downto 0);

begin

process(a)

begin

case a is

when "0000"=> y<="0111111";

when "0001"=> y<="0000110";

when "0010"=> y<="1011011";

when "0011"=> y<="1001111";

when "0100"=> y<="1100111";

when "0101"=> y<="1101101";

when "0110"=> y<="1111100";

when "0111"=> y<="0000111";

when "1000"=> y<="1111111";

when "1001"=> y<="1101111";

end case;

end process;

end Behavioral;