Half adder

Half adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Halfadder is

    Port ( aa,bb : in std_logic;

           sum,carry : out std_logic);

end Halfadder;

architecture Behavioral of Halfadder is

component anding is

port(a,b:in std_logic;

                 y: out std_logic);

end component;

component xoring is

port(x,y:in std_logic;

                 p:out std_logic);

end component;

begin

u1:anding port map(aa,bb,carry);

u2:xoring port map(aa,bb,sum);

end Behavioral;