Comparator:

Comparator:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity comparator is

    Port ( a,b : in std_logic_vector(3 downto 0);

           agtb,altb,aeqb : out std_logic);

end comparator;

architecture Behavioral of comparator is

begin

process(a,b)

begin

for i in 3 downto 0 loop

if(a(i)='1' and b(i)='0')then

agtb<='1';

aeqb<='0';

altb<='0';

exit;

elsif(a(i)='0' and b(i)='1')then

agtb<='0';

altb<='1';

aeqb<='0';

exit;

elsif(i=0)then

agtb<='0';

altb<='0';

aeqb<='1';

end if;

end loop;

end process;

end Behavioral;