BCD counter

BCD  counter:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bcdcounter is

    Port ( clk,rst : in std_logic;

           y : out std_logic_vector(3 downto 0));

end bcdcounter;

architecture Behavioral of bcdcounter is

signal count:std_logic_vector(3 downto 0):=X"0";

begin

y<=count;

process(clk,rst)

begin

if(rst='1')then

count<=X"0";

elsif(count="1001")then

count<=X"0";

elsif(clk='1' and clk'event)then

count<=count+X"1";

end if;

end process;

end Behavioral;